1. Technical Field
The present invention relates to a method and system for maintaining cache coherency in general and, in particular, to a method and system for maintaining cache coherency within a data-processing system. Still more particularly, the present invention relates to a method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system.
2. Description of the Prior Art
A data-processing system typically includes a processor coupled to a variety of storage devices arranged in a hierarchical manner. Hardware and/or software can dynamically allocate parts of the storage devices within the hierarchy for addresses deemed most likely to be accessed soon. The type of storage employed in each hierarchical level relative to the processor normally is determined by balancing the requirements for speed, capacity, and costs.
In addition to a main memory, a commonly employed storage device in the hierarchy includes a high-speed memory known as a cache memory. A cache memory speeds the apparent access times of the relatively slower main memory by retaining the words that the processor most likely is to access again soon, and making the words available to the processor at a much lower latency. As such, cache memory enables relatively fast access to a subset of data and/or instructions that were recently transferred from the main memory to the processor, and thus improves the overall speed of the data-processing system.
A two-level cache memory hierarchy is a cache memory system consisting of two cache memories, each having a different size and speed. Typically, the first cache memory, commonly known as the primary cache or level one (L1) cache, has a faster access time and a higher cost per bit, while the second cache memory, commonly known as the secondary cache or level two (L2) cache, has a slower access time but also a lower cost per bit. In most cases, the smaller and faster primary cache is on-chip, while the larger and slower secondary cache is off-chip, although an on-chip secondary cache also is quite common in some high-performance processor designs nowadays.
In order to maintain a coherent memory system, the same copy of information must be provided to all memory devices within the memory hierarchy for allowing synchronization and cooperative usage of resource sharing. Otherwise, problems will occur when an old or stale copy of information is utilized inadvertently. Hence, under a scheme called inclusion, the primary cache normally is designed to always contain a subset of data stored in the secondary cache. This inclusion scheme provides a certain level of redundancy between the primary cache and the secondary cache so that the bus traffic to the primary cache may be reduced.
In addition, a common goal of any cache memory implementation is to minimize the amount of cache directory space required for a given-size cache memory. This typically is achieved by sectoring the cache memory such that each directory entry represents two or more cache sectors. A sectored cache memory performs bulk data transfers with a shared memory, but subdivides each receiving cache line into sectors of smaller units of data when sharing occurs.
Under the inclusion scheme mentioned above, a traditional sectored secondary cache utilizes one bit, commonly known as an inclusivity bit, per sector to indicate if that particular sector also is present in the primary cache. For example, a secondary cache having four sectors would take a total of four bits to define the inclusivity status of all four cache sectors. Despite the fact that the inclusion scheme under a traditional sectored cache presents a very accurate view of the inclusivity status of each sector, it is desirable to provide a pseudo inclusivity scheme that requires fewer directory bits and simplifies decoding, thus allowing for a smaller cache directory with higher operating frequencies.